Semiconductor

INDUSTRY
PAIN POINTS

• High throughput, tight takt time

  01

  Packaging, sorting, and testing equipment demand millisecond-level vision response. Any latency directly leads to throughput loss.

  Why us

  Hardware-level parallel computing
  Based on Mega Phase hardware computational imaging technology (HWCI) and pixel-level parallel computing by FPGA. Image reconstruction offloads entirely from the host IPC, ensuring deterministic, real-time synchronization  
  
  Instantaneous Output
  Analysis is completed autonomously within the camera. By outputting high-resolution results directly with millisecond-level feedback, our systems perfectly match the cadence of high-speed sorters and testers.

• Multi-layered and high-eflective materials

  02

  Wafer surfaces, lead frames, and gold wires are extremely reflective. This causes tiny scratches, chipping, or foreign objects to be easily obscured by complex background textures.

  Why us

  High Dynamic Range (HDR) imaging
  Our adaptive Single-Frame HDR suppresses glare from wire bonds and solder balls while restoring shadow details. This helps accurately identify micron-level defects.
  
  Authentic 3D Reconstruction 
  Proprietary optical algorithms isolate surface reflection properties. Even when dealing with complex, high-transparency films, our technology extracts authentic 3D point cloud features and textures.  
  
  Ultra-high resolution
  With up to 20MP CMOS sensors, we achieve 2x2 pixel-level sensitivity for tiny dead-pixel detection, ensuring the highest reliability for wafers and packaged components.

• Compact footprint complicates integration

  03

  Space within semiconductor equipment is extremely constrained. It imposes stringent requirements for component miniaturization and minimal computing occupation.

  Why us

  All-in-one design
  Our highly integrated design combines image acquisition, processing, and lighting control into a single unit. By eliminating bulky external controllers, we significantly reduce the system's physical footprint.  

  
  Rapid scalability 
  Simple physical integration combined with high product consistency drastically shortens equipment debugging and line expansion cycles, lowering overall engineering costs.