Mega Phase Next-gen 3D Camera for Wafer Bumping Inspection

As the bedrock of all integrated circuits (ICs), wafers serve as the fundamental physical medium for nearly all smart devices and computing systems. To establish electrical and physical connections between a chip and the external environment, bumping is a critical process. This involves fabricating tens of thousands of microscopic circuitry nodes on the wafer surface. The bumping process typically begins with coating and photolithography to define precise patterns; then electroplating or ball placement to form micron-scale metal protrusions that are then reflowed into standard spherical or quasi-spherical shapes. In advanced packaging, copper pillar bump diameters typically range from 40 µm to 80 µm, though they can shrink to as small as 10 µm for high-end applications.

The better interconnect density and signal transmission efficiency make bumping indispensable for High-Performance Computing (HPC) chips, such as CPUs, GPUs, and AI processors. Compared to traditional methods, the area-array layout of dense bumps achieves higher I/O density and shorter electrical paths.

Consequently, optimal electrical connection requires increasingly stringent quality control. The height, diameter, pitch (true position), and coplanarity of every single bump must be verified. Given the microscopic dimensions, ultra-fine pitch, and highly reflective metallic surfaces, conventional lighting often triggers intense specular reflections, complex halation interference, or shadowing. Without uniform and clear imaging, it is impossible to robustly capture critical features such as contours, coplanarity, missing bumps, or bridging, significantly increasing the difficulty of measurement and the risk of false call rates.

Taking a 12'' wafer as an example, thousands of bumps must be inspected, and each is 70 μm in height, 75 μm in diameter, and has a 150 μm pitch. To ensure optimal electrical connection, the automated optical inspection vision solution is expected to meet the following stringent process tolerances:

• Height tolerance (relative to reference plane): ≤ ±3 um

• Diameter tolerance ≤ ±2 um

• Pitch tolerance (true position) ≤ 3 um

• Global coplanarity tolerance ≤ 3 um

We provide a 21-megapixel area-scan 3D structured light camera with a 14.6 × 11.7 mm field of view (FOV), delivering over 200 valid pixels per individual bump. The camera achieves:

• XY interval: 2.85 μm

• XY repeatability ≤ 0.2 μm

• Z repeatability ≤50 nm (1σ)

Figure 2: Camera setup diagram

Figure 2 illustrates the camera configuration with an automated solution in operation: the wafer is placed horizontally on a high-precision motion stage, bump-side up. The high-speed camera is secured to a customized mount at a constant working distance. Once data acquisition and on-camera pre-processing for a single FOV are complete, the wafer indexes to the next measurement position.

To address the measurement difficulties on the tiny, spherical top surfaces of the bump, our powerful sensor is equipped with strong electro-optical specs: Temporal noise<3.5 e^- (rms), Full-well capacity (FWC) ≥32 ke^-, Dynamic range >68 dB. The high signal-to-noise ratio ensures stable capture of tiny micro-bump features, including spherical and edge profiles; the wide dynamic range effectively prevents local overexposure or underexposure caused by the wafer's reflective surface and bumps. In summary, the system delivers high image quality. To further reduce measurement errors arising from parallax, magnification variation, and lens distortion, the camera is equipped with a high-precision bio-telecentric lens.

Notably, the camera features four integrated projectors that cast fringes from different orientations in an alternating sequence. This ensures the acquisition of high-quality point cloud data, as shown in Figure 3.

Figure 3: The camera captures a crisp image for judging presence/absence, excessive/insufficient bump height.

Compared to traditional single-projector structured light systems, which are prone to high-reflection interference, or 3D line-scan solutions limited by single/dual-view perspectives and poor reconstruction of spherical geometries, this multi-orientation projection effectively compensates for shadows and specular reflections while suppressing stray light. The resulting point cloud data is stable, shadow-free, and high-fidelity, providing a reliable foundation for subsequent high-precision metrology.

In high-volume semiconductor manufacturing, high-precision inspection must be achieved in tandem with high throughput requirements. Traditional solutions often rely on the transmission of massive raw images and complex host computer algorithms, leading to a significant increase in Cycle Time (CT) and a failure to meet the throughput requirement of 5–10 Wafers Per Hour (WPH).

To address this challenge, we adopt a hardware computing (HWCI) architecture based on FPGA technology and integrate an industry-leading frame rate image sensor: exposure can be completed in less than 200 milliseconds, and 3D reconstruction is achievable onboard the camera via a high-performance FPGA chip—only the computed point cloud map needs to be output, with 3D reconstruction for a single field of view finished in less than 500 milliseconds.

In addition, computation, transmission and motion can be executed in full parallel. Collectively, bump inspection for an entire 12’’ wafer can be completed within 250 seconds, which enables us to stably meet the 5–10 WPH throughput requirement while ensuring uncompromised measurement accuracy and data quality

Figure 4: A single snapshot comes to 2D, 3D, and 2D+3D images

As we emphasized before, with millions of micro-bumps on a wafer, every single bump matters for the final packaging yield. Each bump demands a strict dual inspection: precise 2D vision for position and diameter, and high-resolution 3D vision for accurate height and coplanarity. Traditional approaches rely on multiple steps or separate systems, adding complexity and inefficiency to already space-limited clean room operations.

This is precisely the tailored breakthrough of our product for semiconductor customers — our camera can simultaneously output high-resolution 2D grayscale images and 3D point cloud data, with Pixel-level Alignment achieved for the two datasets. As shown in Figure 4 below, this enables you to implement a one-stop verification logic: by cross-referencing 2D defect features (e.g., diameter, pitch, bump positional offset, surface defects, and other 2D characteristics) with 3D topographical features (e.g., height, coplanarity, and other 3D characteristics), you can swiftly validate product quality.

The system performs 2D and 3D metrology synchronously. Since 2D inspection is completed within the time frame of the 3D process, the standard throughput is governed solely by the peak efficiency of the 3D measurement, enabling a capacity of 10 to 14 12'' wafers per hour (WPH).

Furthermore, the camera incorporates a range of unique, patented hardware features that enable many tasks that used to be handled by the host PC to be executed directly on the device. By offloading these processes to the hardware level, the system further minimizes the vision system’s impact on cycle time. This helps customers to flexibly deploy with specialized, project-specific functions on the upper-level system as needed.